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Freescale Semiconductor Technical Data

Document Number: MPC17531A

Rev. 4.0, 5/2009

700 mA Dual H-Bridge Motor Driver with 3.0 V Compatible Logic I/O

The 17531A is a monolithic dual H-Bridge power IC ideal for

portable electronic applications containing bipolar step motors and/or brush DC-motors (e.g., cameras and disk drive head positioners).The 17531A operates from 2.0 V to 8.6 V using the internal charge pump, with independent control of each H-Bridge via parallel MCU interface. The device features built-in shoot-through current protection and an undervoltage shutdown function.

The 17531A has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The 17531A has a low total RDS(ON) of 1.2 Ω (max @ 25°C).

The 17531A efficiently drives many types of micromotors with low power dissipation owing to its low output resistance and high output slew rates. The H-Bridge outputs can be independently pulse width modulated (PWM’ed) at up to 200 kHz for speed/torque and current control.Features•••••••••

Low Total RDS(ON) 0.8 W (Typ), 1.2 Ω (Max) @ 25°COutput Current 0.7 A (DC)

Shoot-Through Current Protection CircuitPWM Control Input Frequency up to 200 kHzBuilt-In Charge Pump CircuitLow Power Consumption

Undervoltage Detection and Shutdown CircuitPower Save Mode with Current Draw ≤ 2.0 μA

Pb-Free Packaging Designated by Suffix Codes EV and EP

17531A

DUAL H-BRIDGE

VMFP SUFFIXEV SUFFIX (PB-FREE)98ASA10616D20-TERMINAL VMFPQFN SUFFIXEP SUFFIX (PB-FREE)98ARL10577D24-TERMINAL QFNORDERING INFORMATION

Device MPC17531AEV/ELMPC17531AEP/R2

Temperature Range (TA)-20°C to 65°C

Package20 VMFP24 QFN

3.0 V5.0 V17531AVDDVMC1LC1HC2LOUT1AC2HCRESOUT1BIN1AOUT2AIN1BOUT2BIN2AIN2BPSAVEGNDBipolarStepMotorSNMCU Figure 1. 17531A Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.

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INTERNAL BLOCK DIAGRAM

CRESC2HC1HC1LC2LLow-VoltageShutdownChargePumpVDDVM1IN1AH-BridgeIN1BVDDLevel Shifter PredriverOUT1AOUT1B PGND1VM2ControlLogicPSAVEIN2AOUT2AH-BridgeIN2BOUT2BLGNDPGND2 Figure 2. 17531A Simplified Internal Block Diagram

17531A

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Analog Integrated Circuit Device Data

Freescale Semiconductor

TERMINAL CONNECTIONS

VDDIN1AIN1B12345671020191817161514131211LGNDIN2AIN2BVM2OUT2BPGND2OUT1BC2LC1LC1HPSAVEOUT2APGND1OUT1AVM1CRESC2H Figure 3. 17531A, 20-Terminal VMFP Connections

Table 1. 17531A, 20-Terminal VMFP Definitions

A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10.

Terminal Number

12345671011121314151617181920

Terminal NameVDDIN1AIN1BPSAVEOUT2APGND1OUT1AVM1

CRES

Formal NameLogic SupplyLogic Input Control 1ALogic Input Control 1B

Power SaveH-Bridge Output 2APower Ground 1H-Bridge Output 1AMotor Drive Power Supply 1Predriver Power SupplyCharge Pump 2HCharge Pump 1HCharge Pump 1LCharge Pump 2LH-Bridge Output 1BPower Ground 2H-Bridge Output 2BMotor Drive Power Supply 2Logic Input Control 2BLogic Input Control 2A

Logic Ground

Definition

Control circuit power supply terminal.

Logic input control of OUT1A (refer to Table 6, Truth Table, page 9).Logic input control of OUT1B (refer to Table 6, Truth Table, page 9).Logic input controlling power save mode.Output A of H-Bridge channel 2.High-current power ground 1.Output A of H-Bridge channel 1.

Positive power source connection for H-Bridge 1 (Motor Drive Power Supply).Internal triple charge pump output as predriver power supply.Charge pump bucket capacitor 2 (positive pole).Charge pump bucket capacitor 1 (positive pole).Charge pump bucket capacitor 1 (negative pole).Charge pump bucket capacitor 2 (negative pole).Output B of H-Bridge channel 1.High-current power ground 2.Output B of H-Bridge channel 2.

Positive power source connection for H-Bridge 2 (Motor Drive Power Supply).Logic input control of OUT2B (refer to Table 6, Truth Table, page 9).Logic input control of OUT2A (refer to Table 6, Truth Table, page 9).Low-current logic signal ground.

C2HC1HC1LC2LOUT1BPGND2OUT2BVM2IN2BIN2ALGND

17531A

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TERMINAL CONNECTIONS

IN1BIN1AIN2A21

242322

NCPSAVEOUT2APGND1OUT1A

123456

IN2B19

181716

VDDTransparent Top View of Package

LGNDVM2NCOUT2BPGND2OUT1BC2L

MPC17530EP

151413

7101112

NCC2HVM1 Figure 4. 17531A, 24-Terminal QFN Connections

Table 2. 17531A, 24-Terminal QFN Definitions

A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10.

Terminal Number1, 6, 7, 17

23451011121314151618192021222324

Terminal NameNCPSAVEOUT2APGND1OUT1AVM1CRESC2HC1HC1LC2LOUT1BPGND2OUT2BVM2IN2BIN2ALGNDVDDIN1AIN1B

Formal NameNo ConnectPower SaveH-Bridge Output 2APower Ground 1H-Bridge Output 1AMotor Drive Power Supply 1Predriver Power SupplyCharge Pump 2HCharge Pump 1HCharge Pump 1LCharge Pump 2LH-Bridge Output 1BPower Ground 2H-Bridge Output 2BMotor Drive Power Supply 2Logic Input Control 2BLogic Input Control 2A

Logic GroundLogic SupplyLogic Input Control 1ALogic Input Control 1B

This terminal is not used.

Logic input controlling power save mode.Output A of H-Bridge channel 2.High-current power ground 1.Output A of H-Bridge channel 1.

Positive power source connection for H-Bridge 1 (Motor Drive Power Supply).Internal triple charge pump output as pre-driver power supply.Charge pump bucket capacitor 2 (positive pole).Charge pump bucket capacitor 1 (positive pole).Charge pump bucket capacitor 1 (negative pole).Charge pump bucket capacitor 2 (negative pole).Output B of H-Bridge channel 1.High-current power ground 2.Output B of H-Bridge channel 2.

Logic input control of OUT1A (refer to Table 6, Truth Table, page 9).Logic input control of OUT1B (refer to Table 6, Truth Table, page 9).

Definition

17531A

CRESC1HC1L4

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Analog Integrated Circuit Device Data

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MAXIMUM RATINGS

Table 3. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.

Ratings

Motor Supply VoltageCharge Pump Output VoltageLogic Supply VoltageSignal Input VoltageDriver Output Current ContinuousPeak (1)ESD Voltage

Human Body Model (2)Machine Model (3)

Operating Junction TemperatureOperating Ambient TemperatureStorage Temperature RangeThermal Resistance (4)Power Dissipation (5)

WMFPQFN

Terminal Soldering Temperature (6)

Notes

1.TA = 25°C. Pulse width = 10 ms at 200 ms intervals.2.3.4.5.6.

ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).For QFN only, mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB).TA = 25°C.

Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.

TSOLDERVESD1VESD2TJTATSTGRθJAPD

1.02.5260

°C

±1200± 150-20 to 150-20 to 65-65 to 150

°C°C°C°C/WW

IOIOPK

0.71.4

SymbolVM

Value-0.5 to 11.0-0.5 to 14.0-0.5 to 5.0-0.5 to VDD + 0.5

UnitVVVVA

RES

VDDVIN

17531A

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STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics

Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

POWER INPUT

Motor Supply Voltage (Using Internal Charge Pump) (7)Motor Supply Voltage (CRES Applied Externally) (8)

Gate Drive Voltage - Motor Supply Voltage (CRES Applied Externally) (9)Logic Supply Voltage

Driver Quiescent Supply CurrentNo Signal InputPower Save Mode

Logic Quiescent Supply CurrentNo Signal Input (10)Power Save Mode

Operating Power Supply Current Logic Supply Current (11)

Charge Pump Circuit Supply Current (12) Low VDD Detection Voltage (13)Driver Output ON Resistance (14)GATE DRIVE

Gate Drive Voltage (12)

No Current Load

Gate Drive Ability (Internally Supplied)

VM-CPVM-NCP

2.0–5.02.7

5.0–6.03.0

8.610–3.6

VVVVμA

––

1001.0

Symbol

Min

Typ

Max

Unit

VCRES - VM

VDD

QMQM-PSAVEQVDDI

QVDD-PSAVE

I I

––

1.01.0

VDD

ICRES

––1.0–

––1.60.8

3.00.72.51.2

VOhms

DDDET

RDS(ON)

VCRES

13.5

VCRESload

8.5

CCP

0.01

9.20.1

–1.0

CRES = -1.0 mA

Recommended External Capacitance (C1L – C1H, C2L – C2H, CRES–GND)Notes7.8.9.10.11.12.13.14.

μF

Gate drive voltage VCRES is generated internally. 2 x VDD + VM must be < VCRES max (13.5 V).V

No internal charge pump used. CRES is applied from an external source.

RDS(ON) is not guaranteed if CRES - VM < 5.0 V. Also, function is not guaranteed if CRES - VM < 3.0 V.I

QVDD includes the current to pre-driver circuit.

I VDD includes the current to predriver circuit at fIN = 100 kHz.At fIN = 20 kHz.

Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. VCRES is

applied from an external source. 2 x VDD + VM must be < CRES max (13.5 V).IO = 0.7 A source + sink.

17531A

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Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics (continued)

Characteristic

CONTROL LOGICLogic Input Voltage

Logic Inputs (2.7 V < VDD < 3.3 V)High-Level Input VoltageLow-Level Input VoltageHigh-Level Input CurrentLow-Level Input Current

PSAVE Terminal Input Current Low

VIHVILIIHIILIIL- PSAVE

VDD x 0.7

––-1.0–

––––50

–VDD x 0.31.0–100

VVμAμAμA

VIN

–

Symbol

Min

Typ

Max

Unit

VDD

17531A

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DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristic

INPUT

Pulse Input FrequencyInput Pulse Rise Time (15)Input Pulse Fall Time (17)OUTPUT

Propagation Delay Time (18)

Turn-ON TimeTurn-OFF Time

Charge Pump Wake-Up Time (19)Low-Voltage Detection TimeNotes15.16.17.18.19.

Time is defined between 10% and 90%.

That is, the input waveform slope must be steeper than this.Time is defined between 90% and 10%.Output load is 8.0 Ω DC.CCP = 0.1 μF.

f INt Rt F

–––

200

(16)

SymbolMinTypMaxUnit

kHzμsμs

1.0 1.0

(16)

t PLHt PHL

t VGON

μs

––––

0.10.11.0–

0.50.53.010

msms

t VDDDET

17531A

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Analog Integrated Circuit Device Data

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TIMING DIAGRAMS

IN1, IN2,PSAVE

DDDETon

50%

VDD

0.8V

2.5V50%

DDDEToff

tPLH

OUTA,OUTB

90%10%

tPHL

VDDDET

90%t

VDDDET

(<1.0 μA)

Figure 5. tPLH, tPHL, and tPZH Timing

Figure 6. Low-Voltage Detection Timing

VDD tVGONV11 VCRES Figure 7. Charge Pump Timing

Table 6. Truth Table

INPUT

PSAVELLLLH

IN1AIN2ALHLHX

IN1BIN2BLLHHX

OUT1AOUT2ALHLZZ

OUTPUT

OUT1BOUT2BLLHZZ

Charge Pump and Low Voltage Detector

RUNRUNRUNRUNSTOP

H = High.L = Low.

Z = High impedance.X = Don’t care.

PSAVE terminal is pulled up to VDD with internal resistance.

17531A

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FUNCTIONAL DESCRIPTIONINTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 17531A is a monolithic dual H-Bridge ideal for

portable electronic applications to control bipolar step motors and brush DC motors such as those found in camera len assemblies, camera shutters, and optical disk drives. The device features an on-board charge pump, as well as built-in shoot-through current protection and undervoltage shutdown.

The 17531A has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The MOSFETs comprising the output bridge have a total source + sink RDS(ON) ≤ 1.2 Ω.

The 17531A can simultaneously drive two brush DC

motors or one bipolar step motor. The drivers are designed to be PWM’ed at frequencies up to 200 kHz.

FUNCTIONAL TERMINAL DESCRIPTION

LOGIC SUPPLY (VDD)

The VDD terminal carries the logic supply voltage and current into the logic sections of the IC. VDD has an

undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input terminals.

MOTOR DRIVE POWER SUPPLY (VM1 AND VM2)

The VM terminals carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or modulated by the IC as it delivers the power to the loads attached between the OUTput

terminals. All VM terminals must be connected together on the printed circuit board.

CHARGE PUMP (C1L AND C1H, C2L AND C2H)

These two pairs of terminals, the C1L and C1H and the C2L and C2H, connect to the external bucket capacitors required by the internal charge pump. The typical value for the bucket capacitors is 0.1 μF.

LOGIC INPUT CONTROL (IN1A, IN1B, IN2A, AND IN2B)

These logic input terminals control each H-Bridge output. IN1A logic HIGH = OUT1A HIGH. However, if all inputs are taken HIGH, the outputs bridges are both tri-stated (refer to Table 6, Truth Table, page 9).

PREDRIVER POWER SUPPLY (CRES)

The CRES terminal is the output of the internal charge pump. Its output voltage is approximately three times of VDD voltage. The VCRES voltage is power supply for the internal predriver circuit of H-Bridges.

POWER SAVE (PSAVE)

The PSAVE terminal is a HIGH = TRUE power save mode input. When PSAVE = HIGH, all H-Bridge outputs (OUT1A, OUT1B, OUT2A, and OUT2B) are tri-stated (High-Z), regardless of logic inputs (IN1A, IN1B, IN2A, and IN2B) states, and the internal charge pump and low voltage detection current are shut off to save power.

POWER GROUND (PGND)

Power ground terminals. They must be tied together on the PCB.

H-BRIDGE OUTPUT (OUT1A, OUT1B, OUT2A, AND OUT2B)

These terminals provide connection to the outputs of each of the internal H-Bridges (see Figure 2, 17531A Simplified Internal Block Diagram, page 2).

LOGIC GROUND (LGND)

Logic ground terminal.

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Analog Integrated Circuit Device Data

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MPC17531AEVEL

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