Memory device and method having multiple internal

专利名称：Memory device and method having multiple

internal data buses and memory bankinterleaving

发明人：Joseph M. Jeddeloh申请号：US1103申请日：20050223公开号：US07209405B2公开日：20070424

专利附图：

摘要：A memory device and method receives write data through a unidirectionaldownstream bus and outputs read data through a unidirectional upstream bus. The

downstream bus is coupled to a pair of internal write data buses, and the upstream bus iscoupled to a pair of internal read data buses. A first set of multiplexers selectively coupleeach of the internal write data buses to any of a plurality of banks of memory cells.Similarly, a second set of multiplexers selectively couple each of the banks of memorycells to any of the internal read data buses. Write data can be coupled to one of thebanks concurrently with coupling read data from another of the banks. Also, write datamay be concurrently coupled from respective write data buses to two different banks,and read data may be concurrently coupled from two different banks to respective readdata buses.

申请人：Joseph M. Jeddeloh

地址：Shoreview MN US

国籍：US

代理机构：Dorsey & Whitney, LLP

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