64Mb H-die SDRAM Specification
54 TSOP-II with Pb-Free
(RoHS compliant)
Revision 1.3August 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
Revision History
Revision 1.0 (September, 2003)
• Finalized
CMOS SDRAM
Revision 1.1 (October, 2003)
Deleted speed -7C and AC parameter notes 5.
Revision 1.2 (May, 2004)
• Added Note 5. sentense of tRDL parameter
Revision 1.3 (August, 2004)
• Corrected typo.
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM
4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address• Four banks operation
• MRS cycle with address key programs -. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh
• 64ms refresh period (4K cycle)
• Pb-free Package
• RoHS compliant
GENERAL DESCRIPTION
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high perfor-mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possibleon every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device tobe useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
K4S640432H-UC(L)75 K4S640832H-UC(L)75 K4S641632H-UC(L)60 K4S641632H-UC(L)70 K4S641632H-UC(L)75
4Mb x 16Orgainization16Mb x 4 8Mb x 8
Max Freq.133MHz(CL=3)133MHz(CL=3)166MHz(CL=3)143MHz(CL=3)133MHz(CL=3)
LVTTL
54pin TSOP(II)
Interface
Package
Organization
16Mx48Mx84Mx16
Row AddressA0~A11A0~A11A0~A11
Column Address
A0-A9A0-A8A0-A7
Row & Column address configuration
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
Package Physical Dimension
CMOS SDRAM
0~8°C0.25TYP0.010#54#280.45~0.750.018~0.0300.05MIN0.002.50( 0 )0.02011.76±0.200.463±0.008#122.62MAX0.89122.220.8750.10MAX0.0040.71( )0.028± 0.10± 0.004#270.210.008± 0.05± 0.0021.000.039± 0.10± 0.004 0.30 -0.050.0040.012+-0.002+0.100.800.031554Pin TSOP(II) Package Dimension
10.160.4000.125+0.075-0.0350.005+0.003-0.0011.20MAX0.047Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAMCMOS SDRAM
I/O ControlLWELDQM
Data Input RegisterBank Select4M x 4 / 2M x 8 / 1M x 16Sense AMP4M x 4 / 2M x 8 / 1M x 164M x 4 / 2M x 8 / 1M x 164M x 4 / 2M x 8 / 1M x 16Refresh CounterOutput BufferRow DecoderRow BufferDQi
Address RegisterCLKADDColumn DecoderCol. BufferLatency & Burst LengthProgramming RegisterLRASLCBRLCKELRASLCBRLWELCASTiming RegisterLWCBRLDQMCLKCKECSRASCASWEL(U)DQM* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
PIN CONFIGURATION (Top view)
x8x4x16
VDDVDDVDD
DQ0DQ0N.CVDDQVDDQVDDQDQ1N.CN.CDQ2DQ1DQ0VSSQVSSQVSSQDQ3N.CN.CDQ4DQ2N.CVDDQVDDQVDDQDQ5N.CN.CDQ6DQ3DQ1VSSQVSSQVSSQDQ7N.CN.CVDDVDDVDDLDQMN.CN.CWEWEWECASCASCASRASRASRASCSCSCSBA0BA0BA0BA1BA1BA1A10/APA10/APA10/AP
A0A0A0A1A1A1A2A2A2A3A3A3VDDVDDVDD
1
23456789101112131415161718192021222324252627
545352515049484746454443424140393837363534333231302928
CMOS SDRAM
x4
VSSN.CVSSQN.CDQ3VDDQN.CN.CVSSQN.CDQ2VDDQN.CVSS
N.C/RFUDQMCLKCKEN.CA11A9A8A7A6A5A4VSS
x8
VSSDQ7VSSQN.CDQ6VDDQN.CDQ5VSSQN.CDQ4VDDQN.CVSS
N.C/RFUDQMCLKCKEN.CA11A9A8A7A6A5A4VSS
x16
VSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8VSS
N.C/RFUUDQMCLKCKEN.CA11A9A8A7A6A5A4VSS
54Pin TSOP (II)(400mil x 875mil)(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
PinCLKCS
Name
System clockChip select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior to new command.Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.Row address : RA0 ~ RA11,
Column address : (x4 : CA0 ~ CA9, x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7)Selects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.Enables column access.
Enables write operation and row precharge.Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
This pin is recommended to be left No Connection on the device.
CKEClock enable
A0 ~ A11BA0 ~ BA1RASCASWEDQMDQ0 ~ X15VDD/VSSVDDQ/VSSQN.C/RFU
Address
Bank select addressRow address strobeColumn address strobeWrite enable
Data input/output maskData input/outputPower supply/groundData output power/groundNo connection
/reserved for future use
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
ABSOLUTE MAXIMUM RATINGS
ParameterVoltage on any pin relative to VSSVoltage on VDD supply relative to VSSStorage temperaturePower dissipationShort circuit current
SymbolVIN, VOUTVDD, VDDQ
TSTGPDIOS
Value-1.0 ~ 4.6-1.0 ~ 4.6-55 ~ +150
150
CMOS SDRAM
UnitVV°CWmA
Note :Permanent device damage may occur if \"ASOLUTE MAXIMUM RATINGS\" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
ParameterSupply voltageInput logic high voltageInput logic low voltageOutput logic high voltageOutput logic low voltageInput leakage current
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
SymbolVDD, VDDQ
VIHVILVOHVOLILI
Min3.02.0-0.32.4--10
Typ3.33.00---Max3.6VDD+0.30.8-0.410
UnitVVVVVuA
12IOH = -2mAIOL = 2mA
3Note
Notes :1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE, DQMAddressDQ0 ~ DQ3
SymbolCCLKCINCADDCOUT
Min2.52.52.54.0
Max4.05.05.06.5
UnitpFpFpFpF
Note1223
Notes :1. -75 only specify a maximum value of 3.5pF
2. -75 only specify a maximum value of 3.8pF3. -75 only specify a maximum value of 6.0pF
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x4, x8)
Parameter
Operating current(One bank active)
Precharge standby current in power-down mode
Precharge standby current in non power-down modeActive standby current in power-down modeActive standby current in non power-down mode(One bank active)
Symbol
Test Condition
Burst length = 1 tRC ≥ tRC(min) IO = 0 mA
CKE ≤ VIL(max), tCC = 10nsCKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
Version75751115
CMOS SDRAM
DC CHARACTERISTICS
UnitNote
ICC1ICC2PICC2PSICC2N
mAmA
1
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS
Input signals are stableICC3PICC3PSICC3N
CKE ≤ VIL(max), tCC = 10nsCKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
mA
63330
mA
25
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC3NS
Input signals are stableICC4ICC5ICC6
IO = 0 mA Page burst
4Banks Activated tCCD = 2CLKs tRC ≥ tRC(min)CKE ≤ 0.2V
CL
Operating current(Burst mode)Refresh currentSelf refresh current
1151351400
mAmAmAuA
1234
Notes :1. Measured with outputs open.
2. Refresh period is 64ms.3. K4S6404(08)32H-TC**4. K4S6404(08)32H-TL**
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
DC CHARACTERISTICS
Parameter
Operating current(One bank active)
Precharge standby current in power-down mode
Precharge standby current in non power-down modeActive standby current in power-down modeActive standby current in non power-down mode(One bank active)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x16 only)
Symbol
Burst length = 1 tRC ≥ tRC(min) IO = 0 mA
CKE ≤ VIL(max), tCC = 10nsCKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
Test Condition
CMOS SDRAM
Version
60
70
75
UnitNote
ICC1ICC2PICC2PSICC2N
140115
1115
110mAmA
1
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS
Input signals are stableICC3PICC3PSICC3N
CKE ≤ VIL(max), tCC = 10nsCKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
mA
63330
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC3NS
Input signals are stableICC4ICC5ICC6
IO = 0 mA Page burst
4Banks Activated tCCD = 2CLKs tRC ≥ tRC(min)CKE ≤ 0.2V
CL
160160
mA
25
Operating current(Burst mode)Refresh currentSelf refresh current
140140
1400
135135
mAmAmAuA
1234
Notes :1. Measured with outputs open.
2. Refresh period is 64ms.3. K4S641632H-TC**4. K4S641632H-TL**
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
ParameterAC input levels (Vih/Vil)
Input timing measurement reference levelInput rise and fall time
Output timing measurement reference levelOutput load condition
3.3V
CMOS SDRAM
Value2.4/0.41.4tr/tf = 1/11.4See Fig. 2
Vtt = 1.4V
UnitVVnsV
1200Ω
Output
870Ω
30pF
VOH (DC) = 2.4V, IOH = -2mAVOL (DC) = 0.4V, IOL = 2mA
Output
Z0 = 50Ω
50Ω
30pF
(Fig. 1) DC output load circuit (Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delayRAS to CAS delayRow precharge timeRow active timeRow cycle time
Last data in to row prechargeLast data in to Active delay
Last data in to new col. address delayLast data in to burst stop
Col. address to col. address delayNumber of valid output data
SymboltRRD(min)tRCD(min)tRP(min)tRAS(min)tRAS(max)tRC(min)tRDL(min)tDAL(min)tCDL(min)tBDL(min)tCCD(min)
CAS latency = 3CAS latency = 2
60
Version
6012181842
70142020491006822 CLK + tRP
11121
657515202045
UnitnsnsnsnsusnsCLK-CLKCLKCLKea
12,552234Note1111
Notes :1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CAS latency=3CAS latency=2CAS latency=3CAS latency=2CAS latency=3CAS latency=2
Symbol
60Min6-Max10005-2.5-2.52.51.511
5-3-33211
6-Min7-70
Max10006-332.52.51.50.81Min7.510
CMOS SDRAM
75
Max10005.46
UnitNote
CLK cycle timeCLK to validoutput delayOutput datahold time
CLK high pulse widthCLK low pulse widthInput setup timeInput hold timeCLK to output in Low-ZCLK to output in Hi-Z
tCCns1
tSACns1,2
tOHtCHtCLtSStSHtSLZ
nsnsnsnsnsns
5.46
ns
233332
CAS latency=3CAS latency=2
tSHZ
Notes :1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Output rise time Output fall time Output rise time Output fall time
Symboltrhtfhtrhtfh
Condition Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V
Min1.371.302.82.0
3.92.9Typ
Max4.373.85.65.0
UnitVolts/nsVolts/nsVolts/nsVolts/ns
Notes331,21,2
Notes :1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.3. Measured into 50pF only, use these values to characterize to.4. All measurements done with respect to VSS.
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
Voltage(V)3.453.303.002.702.501.951.801.651.501.401.000.20
133MHzMinI (mA)---0.35-3.75-6.65-13.75-17.75-20.55-23.55-26.2-36.25-46.5
133MHzMaxI (mA) -1.68 -19.11 -51.87-90.44-107.31-137.9-158.34-173.6-188.79-199.01-241.15-351.68
00-100-200mA-300-400-500-600
Voltage
IOH Min (133MHz)IOH Max (133MHz)
CMOS SDRAM
133MHz Pull-up
0.5
1
1.5
2
2.5
3
3.5
133MHz Pull-down
IOL Characteristics (Pull-down)
Voltage(V)3.453.303.001.951.801.651.501.401.000.850.650.40133MHzMinI (mA)43.92-43.3641.2040.5639.6038.4037.2830.0826.6421.5214.16133MHzMaxI (mA)155.82-153.72148.40146.02141.75136.08131.39105.8493.6675.2549.14250
200
150mA1005000
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (133MHz)IOL Max (133MHz)
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM
Minimum VDD clamp current
(Referenced to VDD)
20
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)0.00.20.40.60.70.80.91.01.21.41.61.82.02.22.42.6I (mA)0.00.00.00.00.00.00.0 0.23 1.34 3.02 5.06 7.35 9.8312.4815.3018.3115
mA10
5
00
1
Voltage
I (mA)
23
Minimum VSS clamp current
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V)-2.6-2.4-2.2-2.0-1.8-1.6-1.4-1.2-1.0-0.9-0.8-0.7-0.6-0.4-0.2 0.0I (mA)-57.23-45.77-38.26-31.22-24.58-18.37-12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.00-10-20mA-30-40-50-60
-3-2-10
Voltage
I (mA)
Rev. 1.3 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
Command
Register
Mode register setAuto refresh
Refresh
Self refresh
EntryExit
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA0,1
CMOS SDRAM
A10/AP
A11,A9 ~ A0
Note
SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t care, H=Logic high, L=Logic low)
HHLHHHH
XHLHXXXXXLHLH
LLLHLLLLLHLXHLHLHL
LLHXLHHHLXVXXHXVXXH
LLHXHLLHHXVXXHXVXH
LHHXHHLLLXVXXHXVXH
XXXXXXXXXXX
VXVVV
OP code
XX
Row addressLHLHXLHX
X
ColumnaddressColumnaddress
1,2333344,544,56
Bank active & row addr.Read &
column addressWrite &
column addressBurst stopPrechargeClock suspend oractive power down
Bank selectionAll banks
EntryExitEntry
Precharge power down mode
Exit
DQM
No operation command
Auto precharge disableAuto precharge enableAuto precharge disableAuto precharge enable
HHLHLHH
X
XVX
XX
7
X
Notes :1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by \"Auto\". Auto/self refresh can be issued only at all banks precharge state.4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are \"Low\" at read, write, row active and precharge, bank A is selected.
If both BA0 is \"Low\" and BA1 is \"High\" at read, write, row active and precharge, bank B is selected. If both BA0 is \"High\" and BA1 is \"Low\" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are \"High\" at read, write, row active and precharge, bank D is selected. If A10/AP is \"High\" at row precharge, BA0 and BA1 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.3 August 2004
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